One known technique for converting a binary coded signal to an output signal having a binary code of base K (e.g., for converting a binary coded signal to a binary coded decimal signal, in which case K = 10) is reported by John F. Couleur in the December 1958 issue of the IRE Transactions on Electronic Computers, Volume EC-7, No. 7. For conversion into binary coded decimal, the prior art technique basically involves sequentially supplying bits of the binary coded input signal to the least significant bit position of the lowest order register of a plurality of cascaded four-bit shift registers. The bits are entered in order, with the most significant bit being entered first. After each bit has been entered the contents of each register are examined and, prior to the next shift, the binary value 0011 is added to the register contents. In response to the sum of the register contents and the binary value 0011 being less than the binary value 1000, no change is made in the contents of a particular register. However, if the sum of the register contents and the binary value 0011 is greater than the binary value 1000, the binary value 0011 is added to the register contents.
One prior art device for implementing the technique disclosed by Couleur is found on page 240 of the Texas Instruments publication entitled "Designing With Integrated Circuits". This prior art implementation utilizes relatively straightforward apparatus for adding the register contents with the values 0011 or 0000, depending upon whether the register contents are greater than 0100 or less than 0101. In particular, a logic network is provided to sense the contents of each register to determine if they are greater than 0100 or less than 0101. In response to the register contents being greater than 0100 the register contents are added to the binary value 0011 in a binary adder; the same binary adder adds the register contents to 0000 in response to the register contents being less than 0101. The logic network required for each register includes two NAND gates having two inputs, one NAND gate having three inputs, and an inverter. Hence, the prior art device uses a relatively large number of components to test the value of each register. The large number of components has a tendency to reduce the reliability of the device, as well as making the device somewhat difficult to construct and troubleshoot. Further, if it is desirable to perform a conversion from a binary coded signal to a binary coded signal having a base other than the ten's base, the conversion can be effected only by replacing each of the logic networks associated with each register. Such a replacement is necessary because it is necessary to test the contents of the register against a different number, depending upon the order to which the binary signal is to be converted.
It is, accordingly, an object of the present invention to provide a new and improved apparatus for converting binary coded input signals into binary coded output signals having an order greater than two.
It is another object of the invention to provide a new and improved binary to binary coded decimal converter wherein the value of each decade is selectively added to the binary value 0011, depending upon whether the value of the decade is greater than 0100 or less than 0101.
A further object of the invention is to provide a new and improved binary to binary coded decimal converter wherein a relatively small amount of hardware is used to determine if the signal valve for each decade is equal to or greater than 0101, thereby to provide increased reliability and ease of troubleshooting.
An additonal object of the invention is to provide a new and improved apparatus for converting a binary coded input signal to an output signal having a binary code of base K, where K is greater than two, wherein the apparatus is readily adapted to convert the input signal to output signals of different bases.